1. Technical Field
The present invention relates generally to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a data storage device including the same.
2. Related Art
In general, a semiconductor memory device is classified into a volatile memory device or a nonvolatile memory device. The volatile memory device loses data stored therein when the power supply is removed, and the nonvolatile memory device maintains data stored therein even though the power supply is removed. The nonvolatile memory device may include various types of memory cells.
The nonvolatile memory device may be further classified into a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change memory device using chalcogenide alloys, a resistive RAM (ReRAM) using transition metal oxide and the like, depending on the structure of memory cells.
Among the nonvolatile memory devices, the flash memory device is typically classified into a NOR flash memory device and a NAND flash memory device, depending on the connection state between memory cells and a bit line. The NOR flash memory device has a structure in which two or more memory cell transistors are connected in parallel to one bit line, which leads to it having excellent random access time characteristics. On the other hand, the NAND flash memory device has a structure in which two or more memory cell transistors are connected in series to one bit line. Such a structure is referred to as a cell string, and one bit line contact is required per one cell string. Such structure allows the NAND flash memory device to have excellent integration capabilities.
Among the nonvolatile memory devices, the flash memory device performs a program or read operation in a page-wise manner, where one page is defined as a plurality of memory cells, due to the structural characteristics thereof. Memory cells forming one page may be accessed according to column addresses. Data may or may not be stored in memory cells corresponding to some column addresses. However, since latches of data read/write circuits corresponding to the memory cells that may or may not have data stored therein are collectively reset regardless of whether data is stored, the current or time required for the program operation may increase.